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4 adc/8 dac with pll, 192 khz, 24 bit codec preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 features pll generated (32-192khz) or direct master clock low emi design 109 db dac/ 107db adc dynamic range and snr -94db thd+n single 3.3v supply tolerance for 5v logic inputs supports 24-bits and 8 khz - 192 khz sample rates differential adc input single-ended or differential dac output versions log volume control with "auto-ramp" function hardware and software controllable clickless mute software and hardware power-down right justified, left justified, i 2 s and tdm modes master and slave modes up to 16 channel in/out 48-lead lqfp or 64-lead lqfp plastic package applications automotive audio systems home theater systems set-top boxes digital audio effects processors general description the ad193x family are high performance, single-chip codecs that provide 4 adcs with differential input and 8 dacs with either single-ended or differential output using adis patented multibit sigma-delta architecture. an spi? or i 2 c? port is included, allowing a microcontroller to adjust volume and many other parameters. the ad193x family operates from 3.3v digital and analog supplies. the ad193x is available in a 48-lead (se output) or 64-lead (differential output) lqfp package. the ad193x is designed for low emi. this consideration is apparent in both the system and circuit design architectures. by using the on-board pll to derive master clock from l-r clock, the ad193x eliminates the need for a separate high frequency master clock. it can also be used with a suppressed bit clock. the d-a and a-d converters are designed using the latest adi continuous time architectures to further minimize emi. by using 3.3v supplies, power consumption is minimized, further reducing emissions. functional block diagram serial data port ad193x dac dac dac dac dac dac adc adc dac dac adc adc digital filter control port spi / i 2 c digital filter & volume control timing management & control (clock & pll) precision voltage reference sdatain sdataout clocks analog audio inputs analog audio outputs digital audio input/output control data input/output serial data port ad193x dac dac dac dac dac dac adc adc dac dac adc adc digital filter control port spi / i 2 c control port spi / i 2 c digital filter & volume control timing management & control (clock & pll) precision voltage reference sdatain sdataout clocks analog audio inputs analog audio outputs digital audio input/output control data input/output figure 1 rev. pr i information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2005 analog devices, inc. all rights reserved.
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 2 of 30 ad193xspecifications test conditions, unless otherwise noted. performance of all channels is identical (exclusive of the inter-channel gain mismatch and inter-channel phase deviation specif ications). parameter rating supply voltages (avdd, dvdd) 3.3 v case temperature 25c master clock 12.288 mhz (48 khz f s , 256 f s mode) input signal 1.000 khz, 0 dbfs (f ull scale), -1 dbvrms (0.9vrms) input sample rate 48 khz measurement bandwidth 20 hz to 20 khz word width 24 bits load capacitance (digital output) 50 pf load current (digital output) 1 ma or 1.5k ? to ? dvdd supply input voltage hi 2.0 v input voltage lo 0.8 v table 1 analog performance parameter min typ max unit adc resolution (all adcs) 24 bits dynamic range (20 hz to 20 khz, C60 db input) 1 no filter (rms) 102 db with a-weighted filter (rms) 105 db with a-weighted filter (avg) 107 db total harmonic distortion + noise (C1 dbfs) 1 C92 db full-scale input voltage (differential) 1.9 v rms gain error C5.0 +5.0 % interchannel gain mismatch C0.1 +0.1 db offset error C10 0 +10 mv gain drift 100 ppm/c interchannel isolation C110 db cmrr, 100 mv rms, 1 khz 70 db cmrr, 100 mv rms, 20 khz 70 db input resistance 14 k ? input capacitance 10 pf analog-to-digital converters input common-mode bias voltage 1.5 v dynamic range (20 hz to 20 khz, C60 db input) 1 no filter (rms), single-ended version 101 db with a-weighted filter (rms), single-ended version 104 db with a-weighted filter (avg), single-ended version 106 db no filter (rms), differential version 104 db with a-weighted filter (rms), differential version 107 db with a-weighted filter (avg), differential version 109 db total harmonic distortion + noise (0 dbfs) 1 single-ended version C92 db differential version C94 db full-scale output voltage (single-ended version) 0.9 (2.5) v rms (v pp) full-scale output voltage (differential version) 1.8 (5.0) v rms (v pp) digital-to-analog converters gain error -6% tbd +6% % 1 total harmonic distortion + noise and dyn amic range typical specifications are for tw o channels active, max/min are all channel s active.
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 3 of 30 parameter min typ max unit interchannel gain mismatch -0.5 +0.5 db offset error, single-ended version -15 mv offset error, differential version -10 mv gain drift -30 30 ppm/c interchannel isolation 100 db interchannel phase deviation 0 degrees volume control step 0.375 db volume control range 95 db de-emphasis gain error 0.6 db output resistance at each pin 100 ? internal reference voltage, filtr 1.50 v external reference voltage, filtr 0.90 1.50 1.80 v reference common-mode reference output, cm 1.50 v table 2 crystal oscillator parameter min typ max unit transconductance 10 mmhos table 3 digital i/o parameter min typ max unit input voltage hi (v ih ) 2.0 v input voltage lo (v il ) 0.8 v input leakage (i ih @ v ih = 2.4 v) 10 a input leakage (i il @ v il = 0.8 v) 10 a high level output voltage (v oh ) i oh = 4 ma dvdd C 0.5 v low level output voltage (v ol ) i ol = 4 ma 0.5 v input capacitance 5 pf table 4 power supplies parameter min typ max unit voltage, dvdd 3.0 3.3 3.6 v voltage, avdd 3.0 3.3 3.6 v digital current 56 ma digital currentpower-down tbd ma digital currentreset tbd ma analog current 74 ma analog currentpower-down tbd ma supplies analog currentreset tbd ma operationall supplies 429 mw operationdigital supply 185 mw operationanalog supply 244 mw dissipation power-downall supplies tbd mw 1 khz 200 mv p-p signal at analog supply pins tbd db power supply rejection ratio 20 khz 200 mv p-p signal at analog supply pins tbd db table 5
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 4 of 30 temperature range parameter min typ max unit specifications guaranteed 25 c case C40 +105 c ambient functionality guaranteed C40 +125 c case storage C65 +150 c table 6 digital filters mode parameter factor min typ max unit pass band 0.4375 f s 21 khz pass-band ripple 0.015 db transition band 0.5 f s 24 khz stop band 0.5625 f s 27 khz stop-band attenuation 79 db adc decimation filter all modes, typ @ 48 khz group delay 22.9844/ f s 479 s pass band 0.4535 f s 22 khz pass-band ripple 0.01 db transition band 0.5 f s 24 khz stop band 0.5465 f s 26 khz stop-band attenuation 70 db 48 khz mode, typ @ 48 khz group delay 25/ f s 521 s pass band 0.3646 f s 35 khz pass-band ripple 0.05 db transition band 0.5 f s 48 khz stop band 0.6354 f s 61 khz stop-band attenuation 70 db 96 khz mode, typ @ 96 khz group delay 11/ f s 115 s pass band 0.3646 f s 70 khz pass-band ripple 0.1 db transition band 0.5 f s 96 khz stop band 0.6354 f s 122 khz stop-band attenuation 70 db dac interpolation filter 192 khz mode, typ @ 192 khz group delay 8/ f s 42 s table 7 timing specifications parameter comments min max unit t mh mclk high pll mode 15 ns t ml mclk low pll mode 15 ns t mclk mclk period pll mode, 256 f s reference 73 146 ns f mclk mclk frequency pll mode, 256 f s reference 6.9 13.8 mhz t mh mclk high direct 512 f s mode 15 ns t ml mclk low direct 512 f s mode 15 ns t mclk mclk period direct 512 f s mode 36 ns f mclk mclk frequency direct 512 f s mode 27.6 mhz t pdr pd/rst low tbd ns master clock and reset t pdrr pd/rst recovery reset to active output tbd t mclk t cch cclk high tbd ns t ccl cclk low tbd ns spi port t ccp cclk period 50 ns
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 5 of 30 parameter comments min max unit f cclk cclk frequency 20 mhz t cds cdata setup to cclk rising tbd ns t cdh cdata hold from cclk rising tbd ns t cls clatch setup to cclk rising tbd ns t clh clatch hold from cclk falling tbd ns t clh clatch high tbd ns t coe cout enable from cclk falling tbd ns t cod cout delay from cclk falling tbd ns t coh cout hold from cclk falling tbd ns t cots cout three-state from cclk falling tbd ns f scl scl clock frequency 400 khz t sclh scl high 0.6 s t scll scl low 1.3 s t scs setup time relevant for repeated start condition 0.6 s t sch hold time after this period the 1st clock is generated 0.6 s t ds data setup time 100 ns t scr scl rise time 300 ns t scf scl fall time 300 ns t sdr sda rise time 300 ns start condition t sdf sda fall time 300 ns i 2 c port stop condition t scs setup time 0.6 s t dbh dbclk high tbd ns t dbl dbclk low tbd ns f db dbclk frequency tbd ns t dls dlrclk setup to dbclk rising tbd ns slave mode t dlh dlrclk hold from dbclk rising tbd ns master mode t dls dlrclk skew from dbclk falling tbd tbd ns t dds dsdata setup to dbclk rising tbd ns dac serial port t ddh dsdata hold from dbclk rising tbd ns t abh abclk high tbd ns t abl abclk low tbd ns f db abclk frequency tbd ns t als alrclk setup to abclk rising tbd ns slave mode t alh alrclk hold from abclk rising tbd ns master mode t als alrclk skew from abclk falling tbd tbd ns adc serial port t abdd asdata delay from abclk falling tbd ns t axds aauxdata setup to auxbclk rising tbd ns t axdh aauxdata hold from auxbclk rising tbd ns t dxdd dauxdata delay from auxbclk falling tbd ns t xbh auxbclk high tbd ns t xbl auxbclk low tbd ns f xb auxbclk frequency tbd ns t dls auxlrclk setup to auxbclk rising tbd ns auxiliary interface t dlh auxlrclk hold from auxbclk rising tbd ns table 8
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 6 of 30 absolute maximum ratings parameter min max unit analog (avdd) C0.3 +3.6 v digital (dvdd) C0.3 +3.6 v input current (except supply pins) 20 ma analog input voltage (signal pins) C0.3 avdd + 0.3 v digital input voltage (signal pins) C0.3 dvdd + 0.3 v case temperature (operating) C40 +125 c table 9 stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package characteristics parameter min typ max unit ja (thermal resistance [junction to ambient]), 48-lead lqfp 50.1 c/w jc (thermal resistance [junction to case]), 48-lead lqfp 17 c/w ja (thermal resistance [junction to ambient]), 64-lead lqfp 47 c/w jc (thermal resistance [junction to case]), 64-lead lqfp 11.1 c/w note: characteristics are for a 4-layer board table 10
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 7 of 30 figure 2. adc passband filter response, 48 khz figure 3. adc stopband filter response, 48 khz figure 4. dac passband filter response, 48 khz figure 5. dac stopband filter response, 48 khz figure 6. dac passband filter response, 96 khz figure 7. dac stopband filter response, 96 khz
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 8 of 30 figure 8. dac passband filter response, 192 khz figure 9. dac stopband filter response, 192 khz
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 9 of 30 functional overview adcs there are four adc channels in the ad193x configured as two stereo pairs with differential inputs. the adcs can operate at a nominal sample rate of 48, 96 , or 192 khz. the adcs include on- board digital anti-aliasing filters with 79 db stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (48 khz, 96 khz, and 192 khz modes). digital outputs are supplied through two serial data output pins (one for each stereo pair) and a common frame (alrclk) and bit (abclk) clock. alternatively, one of the tdm modes may be used to access up to 16 channels on a single tdm data line. the adcs must be driven from a differential signal source for best performance. the input pins of the adcs connect to internal switched capacitors. to isolate the external driving op amp from the glitches caused by the internal switched capacitors, each input pin should be isolated by using a series-connected external 100 ? resistor together with a 1 nf capacitor connected from each input to ground. this capacitor must be of high quality; for example, ceramic npo or polypropylene film. the differential inputs have a nominal common-mode voltage of 1.5v. the voltage at the common-mode reference pin, cm can be used to bias external op amps to buffer the input signals (see the power supply and voltage reference section). the inputs can also be ac coupled and do not need an external dc bias to cm. a digital high-pass filter can be switched in line with the adcs under serial control to remove residual dc offsets. it has a 1.4 hz, 6 db per octave cutoff at a 48 khz sample rate. the cutoff frequency will scale directly with sample frequency. dacs the ad193x dac channels are arranged as four stereo pairs giving eight analog outputs, either single-ended for minimum external components or differential for improved noise and distortion performance. the dacs include on-board digital reconstruction filters with 70 db stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 khz or 96 khz modes) or 2 (192 khz mode). each channel has its own independently programmable attenuator, adjustable in 255 0.375 db steps. digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (dlrclk) and bit (dbclk) clock. alternatively, one of the tdm modes may be used to access up to 16 channels on a single tdm data line. each output pin has a nominal common-mode dc level of 1.5v and swings 1.27 v for a 0 dbfs digital input signal. a single op amp third order external low-pass filter is recommended to remove high frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion in the case of the differential output part. note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. the voltage at the common-mode reference pin, cm can be used to bias the external op amps that buffer the output signals (see the power supply and voltage reference section). clock signals the on-chip phase locked loop (pll) can be selected to use as its reference the input sample rate from either of the lrclk pins or 256, 384, 512, or 768 times the sample rate, referenced to 48khz mode, from the mclki pin. the default at power-up is 256 f s from mclki. in 96 khz mode, the master clock frequency will stay at the same absolute frequency so the actual multiplication rate will be divided by 2. in 192 khz mode, the actual multiplication rate will be divided by 4. for example, if the ad193x is programmed in 256 f s mode, the frequency of the master clock input would be 256 48 khz = 12.288 mhz. if the ad193x is then switched to 96 khz operation (by writing to the spi or i 2 c port), the frequency of the master clock should remain at 12.288 mhz, which is now 128 f s . in 192khz mode, this would be 64 f s . the internal clock for the adcs is 256 f s for all clock modes. the internal clock for the dacs is 512 f s (48 khz mode), 256 f s (96 khz mode), or 128 f s (192 khz mode). by default, the on-board pll is used to generate this internal master clock from an external clock. a direct 512 f s ( referenced to 48 khz mode) master clock can be used for either the adcs or dacs if selected in pll and clock control register 1. note that it is not possible to use a direct clock for the adcs set to 192khz mode. it is required that the on-chip pll be used in this mode. the pll can be powered down in pll and clock control register 0. to ensure reliable locking when changing pll modes or if the reference clock may be unstable at power-on, the pll should be powered down and then powered back up when the reference clock is stable. the internal mclk can be disabled in pll and clock control register 0 to reduce power dissipation when the ad193x is idle. the clock should be stable before it is enabled. unless a stand- alone mode is selected (see serial control port ), the clock is disabled by reset and must be enabled by writing to the spi or i 2 c port for normal operation. to maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms tie (time interval error). even at these levels, extra noise or tones may appear in the dac outputs if the jitter spectrum contains large spectral peaks. if the internal pll is not being used, it is highly recommended that an independent crystal
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 10 of 30 oscillator generate the master clock. in addition, it is especially important that the clock signal should not be passed through an fpga, cpld, or other large digital chip (such as a dsp) before being applied to the ad193x. in most cases, this will induce clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. when the pll is used, jitter in the reference clock will be attenuated above a certain frequency depending on the loop filter. reset and power-down reset will set all the control registers to their default settings. to avoid pops, reset does not power down the analog outputs. after reset is de-asserted, an initialization routine will run inside the ad193x. this initialization lasts for approximately xx mclks. the power-down bits in the pll and clock control 0, dac control 1, and adc control 1 registers will power down the respective sections. all other register settings are retained. serial control port the ad193x has an spi or i 2 c compatible control port that permits programming and reading back the internal control registers for the adcs, dacs, and clock system. there is also a stand-alone mode available for operation without serial control, configured at reset using the serial control pins. all registers are set to default except internal mclk enable is set to 1 and adc bclk and lrclk master/slave is set by cout/sda. refer to table 10 for details. adc clocks: cin/adr0 cout/sda cclk/scl clatch/ adr1 slave 0 0 0 0 master 0 1 0 0 table 11. stand-alone mode selection the spi control port of the ad1938 and ad1939 is a 4-wire serial control port. the format is similar to the motorola spi format except the input data-word is 24 bits wide. the serial bit clock and latch may be completely asynchronous to the sample rate of the adcs and dacs. figure 10 shows the format of the spi signal. the first byte is a global address with a read/write bit. for the ad193x the address is 0x04, shifted left 1 bit due to the r/ w bit. the second byte is the ad193x register address and the third byte is the data. clatch cclk cin cout d0 d8 d0 d15 d14 d9 d8 t cch t ccl d9 t cds t cdh t cls t clh t cod t cots t ccp t coe figure 10. format of spi signal the i 2 c interface of the ad1936 and ad1937 is a two wire interface consisting of a clock line, scl and a data line, sda. sda is bidirectional and the ad1936 and ad1937 will drive sda either to acknowledge the master, ack, or to send data during a read operation. the sda pin for the i 2 c port is an open drain collector and requires a 1k? pullup resistor. a write or read access occurs when the sda line is pulled low while the scl line is high indicated by start in the timing diagrams. sda is only allowed to change when scl is low except when a start or stop condition occurs as shown in figures 3 and 4. the first eight bits of the access consist of the device address and the r/w bit. the device address consists of an internal built-in address (0x04) and two address pins, ad1 and ad0. the two address pins allow up to four ad1936s and ad1937s to be used in a system. initiating a write operation to the ad1936 and ad1937 involves sending a start condition and then sending the device address with the r/w set low. the ad1936 and ad1937 will respond by issuing an ack to indicate that it has been addressed. the user then sends a second frame telling the ad1936 and ad1937 which register is required to be written to. another ack is issued by the ad1936 and ad1937. finally the user can send another frame with the 8 data bits required to be written to the register. a third ack is issued by the ad1936 and ad1937 after which the user can send a stop condition to complete the data transfer. a read operation requires that the user first write to the ad1936 and ad1937 to point to the correct register and then read the data. this is achieved by sending a start condition followed by the device address frame, with r/w low, and then the register address frame. following the ack from the ad1936 and ad1937 the user must issue a repeated start condition. this is identical to a start condition. the next frame is the device address with r/w set high. on the next frame the ad1936 and ad1937 will output the register data on the sda line. a stop condition completes the read operation. figure 3 and figure 4 show examples of writing to and reading from the dac 1 left volume register (address = 0x06)
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 11 of 30 r/ w 0 sck sda 0 0 0 1 ad1 ad0 0 0 0 0 0 1 1 0 ack. by ad193x start by master d7 d6 d5 d4 d3 d2 d1 d0 ack. by ad193x stop by master sck (continued) sda (continued) frame 1 chip address byte frame 3 data byte to ad193x frame 2 register address byte ack. by ad193x 8 0 3 - 0 0 3 9 figure 11. format of i 2 c write r/ w 0 scl sda 0 0 0 1 ad1 ad0 0 0 0 0 0 1 1 0 ack. by ad193x start by master d7 d6 d5 d4 d3 d2 d1 d0 ack. by ad193x stop by master frame 1 chip address byte frame 2 register address byte ack. by ad193x r/ w 0 scl (continued) sda (continued) 00 0 1 ad1 ad0 repeated start by master frame 3 chip address byte frame 4 register data ack. by ad193x 8 0 3 - 0 0 4 0 figure 12. format of i 2 c read power supply and voltage reference the ad193x is designed for 3.3 v supplies. separate power supply pins are provided for the analog and digital sections. these pins should be bypassed with 100 nf ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. a bulk aluminum electrolytic capacitor of at least 22 f should also be provided on the same pc board as the codec. for critical applications, improved performance will be obtained with separate supplies for the analog and digital sections. if this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. it is important that the analog supply be as clean as possible. the ad1935 (64-pin single-ended version), and the ad1939 and ad1937 (64-pin differential versions) include a 3.3v regulator driver which requires only an external pass transistor and bypass capacitors to make a 5v to 3.3v regulator. if the regulator driver is not used, vsupply, vdrive, and vsense should be connected to dgnd. all digital inputs are compatible with ttl and cmos levels. all outputs are driven from the 3.3 v dvdd supply and are compatible with ttl and 3.3 v cmos levels. the adc and dac internal voltage reference v ref is brought out on filtr and should be bypassed as close as possible to the chip, with a parallel combination of 10 f and 100 nf. any external current drawn should be limited to less than 50 a. the internal reference can be disabled in pll and clock control register 1 and filtr driven from an external source. this can be used to scale the dac output to a power amplifier's clipping level based on its power supply voltage. the adc input gain will also vary by the inverse ratio. the total gain from adc input to dac output will stay constant. the cm pin is the internal common-mode reference. it should be bypassed as close as possible to the chip, with a parallel combination of 10 f and 100 nf. this voltage may be used to bias external op amps to the common-mode voltage of the input and output signal pins. the output current should be limited to less than 0.5 ma source and 2 ma sink.
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 12 of 30 serial data portsdata format the eight dac channels output or accept a common serial bit clock and left-right framing clock to clock in the serial data. the four adc channels output or accept a common serial bit clock and left- right framing clock to clock out the data. the clock signals are all synchronous with the sample rate. in the aux modes, set in adc control 1 and dac control 0, the dacs use the adc serial bit clock and left-right clock as the dac clock pins are used for the auxiliary adc/dac serial clocks. the adc and dac serial data modes default to i 2 s. the ports can also be programmed for left-justified, right-justified and tdm modes. the word width is 24 bits by default and can be programmed for 16 or 20 bits. the normal tdm mode can be daisy-chained with a second ad193x and will support 16 channels at 48 khz, 8 channels at 96 khz or 4 channels at 192 khz. there is also a dual-line tdm mode to support 8 channels at 192 khz. the special auxiliary modes are provided to allow two external stereo adcs and/or two external stereo dacs to be interfaced with the ad193x to provide up to 8 in/12 out operation or 2 ad193xs to be chained for up to 16 in/16 out operation. these modes provide a glueless interface to a single sharc serial port, allowing the dsp to access up to 16 channels of analog i/o. in these modes many pins are redefined, see table 10. see figure 18 for details of these modes. the following figures show the serial mode formats. lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata lrclk bclk sdata left channel right channel left channel right channel msb lsb lsb lsb lsb lsb left justified mode??16 bits to 24 bits per channel i 2 s mode??16 bits to 24 bits per channel right justified mode??select number of bits per channel dsp mode??16 bits to 24 bits per channel notes 1. dsp mode does not identify channel 2. lrclk normally operates at f s except for dsp mode which is 2 f s 3. bclk frequency is normally 64 lrclk but may be operated in burst mode msb msb msb lsb left channel msb lsb msb right channel lsb msb msb 1/f s figure 13. stereo serial modes
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 13 of 30 t dls dbclk dlrclk dsdata left-justified mode dsdata right-justified mode lsb dsdata i 2 s-justified mode t dbh t dbp t dbl t dds msb msb-1 t ddh t dds msb t ddh t dds t dds t ddh t ddh msb t dlh figure 14. dac serial timing t als abclk alrclk asdata left-justified mode asdata right-justified mode lsb asdata i 2 s-justified mode t abh t abp t abl t abdd msb msb-1 msb msb t alh t abdd t abdd figure 15. adc serial timing
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 14 of 30 lrclk bclk data slot 1 left 1 slot 2 right 1 slot 5 right 2 slot 6 32 bclks msb msb?1 msb?2 256 bclks slot 3 slot 4 slot 7 slot 8 lrclk bclk data left 2 lrclk bclk data slot 1 left 1 slot 2 right 1 slot 5 right 2 slot 6 32 bclks msb msb?1 msb?2 256 bclks slot 3 slot 4 slot 7 slot 8 lrclk bclk data left 2 figure 16. adc tdm (8-channel i 2 smode ) lrclk bclk data slot 1 left 1 slot 2 right 1 slot 5 right 2 slot 6 32 bclks msb msb?1 msb?2 256 bclks slot 3 slot 4 slot 7 slot 8 lrclk bclk data left 2 right 3 left 3 right 4 left 4 lrclk bclk data slot 1 left 1 slot 2 right 1 slot 5 right 2 slot 6 32 bclks msb msb?1 msb?2 256 bclks slot 3 slot 4 slot 7 slot 8 lrclk bclk data left 2 right 3 left 3 right 4 left 4 figure 17. dac tdm (8-channel i 2 s mode) fstdm adc l1 adc r1 adc l2 adc r2 aux adc l1 aux adc r1 aux adc l2 aux adc r2 dac l1 dac r1 dac l2 dac l3 dac r3 dac l4 msb tdm 1st ch left right i 2 s-msbright i 2 s-msbleft bclk tdm asdata1 tdm (out) asdata dsdata1 tdm (in) dsdata1 aux lrclk (from aux adc 1) aux bclk (from aux adc 1) aux data in 1 (from aux adc 1) aux data in 2 (from aux adc 2) aux bclk frequency is 64 frame-rate; tdm bclk frequency is 256 frame-rate. t d m i n t e r f a c e a u x - i 2 s i n t e r f a c e msb tdm 8th ch 32 32 msb tdm 1st ch msb tdm 8th ch i 2 s-msbright i 2 s-msbleft dac r2 dac r4 figure 18. aux 256 mode timing (note that the clocks are not to scale)
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 15 of 30 pin function changes in tdm and aux modes pin name stereo modes tdm modes aux modes asdata1 adc1 data out adc tdm data out tdm data out asdata2 adc2 data out adc tdm data in aux data out 1 (to ext. dac 1) dsdata1 dac1 data in dac tdm data in tdm data in dsdata2 dac2 data in dac tdm data out aux data in 1 (from ext. adc 1) dsdata3 dac3 data in dac tdm data in 2 (dual-line mode) aux data in 2 (from ext. adc 2) dsdata4 dac4 data in dac tdm data out 2 (dual-line mode) aux data out 2 (to ext. dac 2) alrclk adc lrclk in/out adc tdm frame sync in/out tdm frame sync in/out abclk adc bclk in/out adc tdm bclk in/out tdm bclk in/out dlrclk dac lrclk in/out dac tdm frame sync in/out aux lrclk in/out dbclk dac bclk in/out dac tdm bclk in/out aux bclk in/out table 12 30mhz 12.288mhz sharc is running in slave mode (interrupt-driven) f s y n c - t d m ( r f s ) r x c l k r x d a t a t f s ( n c ) t x c l k t x d a t a asdata1 alrclk abclk dsdata1 lrclk bclk data mclk aux adc 1 sharc ad193x mclk dsdata2 dlrclk lrclk bclk data mclk aux adc 2 lrclk bclk data mclk aux dac 1 lrclk bclk data mclk aux dac 2 dsdata3 dbclk asdata2 dsdata4 tdm master aux master figure 19. example of aux mode connection to sharc (ad193x as tdm master/aux master shown)
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 16 of 30 pin function descriptions 48-lead lqfp plastic package C ad1936, ad1938 pin no. in/out mnemonic description 1 i agnd analog ground. 2 i mclki/xi master clock inpu t/ crystal oscillator input. 3 i mclk/xo master clock outp ut/ crystal oscillator output. 4 i agnd analog ground. 5 i avdd analog power supply. connect to analog 3.3 v supply. 6 o ol3 dac 3 left output. 7 o or3 dac 3 right output. 8 o ol4 dac 4 left output. 9 o or4 dac 4 right output. 10 i pd/rst power-down reset (active low). 11 i dsdata4 dac input 4 (input to dac 4 l and r). 12 i dgnd digital ground. 13 i dvdd digital power supply. co nnect to digital 3.3 v supply. 14 i dsdata3 dac input 3 (input to dac 3 l and r). 15 i dsdata2 dac input 2 (input to dac 2 l and r). 16 i dsdata1 dac input 1 (input to dac 1 l and r). 17 i/o dbclk bit clock for dacs. 18 i/o dlrclk lr clock for dacs. 19 o asdata2 adc serial data output 2 (adc 2 l and r). 20 o asdata1 adc serial data output 1 (adc 1 l and r). 21 i/o abclk bit clock for adcs. 22 i/o alrclk lr clock for adcs. 23 o cin/adr0 control data input (spi)/address 0 (i 2 c). 24 i cout/sda control data output (spi)/serial data (i 2 c). 25 i dgnd digital ground. 26 i cclk/scl control clock input (spi)/serial clock (i 2 c). 27 i clatch/ adr1 latch input for control data (spi)/address 1 (i 2 c). 28 o ol1 dac 1 left output. 29 o or1 dac 1 right output. 30 o ol2 dac 2 left output. 31 o or2 dac 2 right output. 32 i agnd analog ground. 33 i avdd analog power supply. connect to analog 3.3 v supply. 34 i agnd analog ground. 35 o filtr voltage reference filter capacitor connection. bypass with 10 f||100 nf to agnd. 36 i agnd analog ground. 37 i avdd analog power supply. connect to analog 3.3 v supply. 38 o cm common mode reference filter capacitor connection. bypass with 10 f||100 nf to agnd. 39 i adc1lp adc1 left positive input. 40 i adc1ln adc1 left negative input. 41 i adc1rp adc1 right positive input. 42 i adc1rn adc1 right negative input. 43 i adc2lp adc2 left positive input. 44 i adc2ln adc2 left negative input. 45 i adc2rp adc2 right positive input. 46 i adc2rn adc2 right negative input. 47 o lf pll loop filter, return to avdd. 48 i avdd analog power supply. connect to analog 3.3 v supply. table 13. pin function description48-lead lqfp( ad1936, ad1938)
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 17 of 30 64-lead lqfp plastic package C ad1937, ad1939 pin no. in/out mnemonic description 1 i agnd analog ground. 2 i mclki/xi master clock inpu t/ crystal oscillator input. 3 i mclk/xo master clock outp ut/ crystal oscillator output. 4 i agnd analog ground. 5 i avdd analog power supply. connect to analog 3.3 v supply. 6 o ol3p dac 3 left positive output. 7 o ol3n dac 3 left negative output. 8 o or3p dac 3 right positive output. 9 o or3n dac 3 right negative output. 10 o ol4p dac 4 left positive output. 11 o ol4n dac 4 left negative output. 12 o or4p dac 4 right positive output. 13 o or4n dac 4 right negative output. 14 i pd/rst power-down reset (active low). 15 i dsdata4 dac input 4 (input to dac 4 l and r). 16 i dgnd digital ground. 17 i dvdd digital power supply. co nnect to digital 3.3 v supply. 18 i dsdata3 dac input 3 (input to dac 3 l and r). 19 i dsdata2 dac input 2 (input to dac 2 l and r). 20 i dsdata1 dac input 1 (input to dac 1 l and r). 21 i/o dbclk bit clock for dacs. 22 i/o dlrclk lr clock for dacs. 23 vsupply +5v input to regulator, emitter of pass transistor 24 vsense +3.3v output of regula tor, collector of pass transistor 25 vdrive drive for base of pass transistor 26 o asdata2 adc serial data output 2 (adc 2 l and r). 27 o asdata1 adc serial data output 1 (adc 1 l and r). 28 i/o abclk bit clock for adcs. 29 i/o alrclk lr clock for adcs. 30 i cin/adr0 control data input (spi)/address 0 (i 2 c). 31 i/o cout/sda control data output (spi)/serial data (i 2 c). 32 i dvdd digital power supply. co nnect to digital 3.3 v supply. 33 i dgnd digital ground. 34 i cclk/scl control clock input (spi)/serial clock (i 2 c). 35 i clatch/ adr1 latch input for control data (spi)/address 1 (i 2 c). 36 o ol1p dac 1 left positive output. 37 o ol1n dac 1 left negative output. 38 o or1p dac 1 right positive output. 39 o or1n dac 1 right negative output. 40 o ol2p dac 2 left positive output. 41 o ol2n dac 2 left negative output. 42 o or2p dac 2 right positive output. 43 o or2n dac 2 right negative output. 44 i agnd analog ground. 45 i avdd analog power supply. connect to analog 3.3 v supply. 46 i agnd analog ground. 47 o filtr voltage reference filter capacitor connection. bypass with 10 f||100 nf to agnd. 48 i agnd analog ground. 49 no connect. 50 no connect. 51 i avdd analog power supply. connect to analog 3.3 v supply.
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 18 of 30 pin no. in/out mnemonic description 52 o cm common mode reference filter capacitor connection. bypass with 10 f||100 nf to agnd. 53 i adc1lp adc1 left positive input. 54 i adc1ln adc1 left negative input. 55 i adc1rp adc1 right positive input. 56 i adc1rn adc1 right negative input. 57 i adc2lp adc2 left positive input. 58 i adc2ln adc2 left negative input. 59 i adc2rp adc2 right positive input. 60 i adc2rn adc2 right negative input. 61 o lf pll loop filter, return to avdd. 62 i avdd analog power supply. connect to analog 3.3 v supply. 63 no connect. 64 no connect. table 14. pin function description64-lead lqfp (ad1937, ad1939) 64-lead lqfp plastic package C ad1935 pin no. in/out mnemonic description 1 i agnd analog ground. 2 i mclki/xi master clock inpu t/ crystal oscillator input. 3 i mclk/xo master clock outp ut/ crystal oscillator output. 4 i agnd analog ground. 5 i avdd analog power supply. connect to analog 3.3 v supply. 6 o ol3 dac 3 left output. 7 o no connect. 8 o or3 dac 3 right output. 9 o no connect. 10 o ol4 dac 4 left output. 11 o no connect. 12 o or4 dac 4 right output. 13 o no connect. 14 i pd/rst power-down reset (active low). 15 i dsdata4 dac input 4 (input to dac 4 l and r). 16 i dgnd digital ground. 17 i dvdd digital power supply. co nnect to digital 3.3 v supply. 18 i dsdata3 dac input 3 (input to dac 3 l and r). 19 i dsdata2 dac input 2 (input to dac 2 l and r). 20 i dsdata1 dac input 1 (input to dac 1 l and r). 21 i/o dbclk bit clock for dacs. 22 i/o dlrclk lr clock for dacs. 23 vsupply +5v input to regulator, emitter of pass transistor 24 vsense +3.3v output of regula tor, collector of pass transistor 25 vdrive drive for base of pass transistor 26 o asdata2 adc serial data output 2 (adc 2 l and r). 27 o asdata1 adc serial data output 1 (adc 1 l and r). 28 i/o abclk bit clock for adcs. 29 i/o alrclk lr clock for adcs. 30 i cin control data input (spi) 31 i/o cout control data output (spi) 32 i dvdd digital power supply. co nnect to digital 3.3 v supply. 33 i dgnd digital ground. 34 i cclk control clock input (spi) 35 i clatch latch input for control data (spi)
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 19 of 30 pin no. in/out mnemonic description 36 o ol1 dac 1 left output. 37 o no connect. 38 o or1 dac 1 right output. 39 o no connect. 40 o ol2 dac 2 left output. 41 o no connect. 42 o or2 dac 2 right output. 43 o no connect. 44 i agnd analog ground. 45 i avdd analog power supply. connect to analog 3.3 v supply. 46 i agnd analog ground. 47 o filtr voltage reference filter capacitor connection. bypass with 10 f||100 nf to agnd. 48 i agnd analog ground. 49 no connect. 50 no connect. 51 i avdd analog power supply. connect to analog 3.3 v supply. 52 o cm common mode reference filter capacitor connection. bypass with 10 f||100 nf to agnd. 53 i adc1lp adc1 left positive input. 54 i adc1ln adc1 left negative input. 55 i adc1rp adc1 right positive input. 56 i adc1rn adc1 right negative input. 57 i adc2lp adc2 left positive input. 58 i adc2ln adc2 left negative input. 59 i adc2rp adc2 right positive input. 60 i adc2rn adc2 right negative input. 61 o lf pll loop filter, return to avdd. 62 i avdd analog power supply. connect to analog 3.3 v supply. 63 no connect. 64 no connect. table 15. pin function description64-lead lqfp (ad1935) pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 top view (not to scale) agnd avdd or2 ol2 or1 ol1 cclk/scl clatch /adr1 l f agnd avdd ol3 or3 ol4 or4 pd/rst dsdata4 d s d a t a 3 d s d a t a 2 d s d a t a 1 a v d d agnd mclki/xi mclko/xo ad193x dgnd dgnd a d c 2 r n a d c 2 r p a d c 2 l n a d c 2 l p a d c 2 r n a d c 1 r p a d c 1 l n a d c 1 l p c m filtr agnd a v d d d v d d d b c l k d l r c l k a s d a t a 2 a s d a t a 1 a b c l k a l r c l k c o u t / s d a c i n / a d r 0 single-ended output agnd figure 20. single-ended output 48-lead lqfp (ad1936, ad1938) preliminary
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 20 of 30 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 17 18 19 20 21 22 23 24 9 10 11 12 1 2 3 4 5 6 7 8 60 59 58 57 56 51 50 49 55 54 53 52 14 15 16 13 29 30 31 32 48 47 46 45 64 63 62 61 d v d d d b c l k d l r c l k d s d a t a 3 d s d a t a 2 d s d a t a 1 a s d a t a 2 a s d a t a 1 a b c l k a l r c l k c o u t / s d a c i n / a d r 0 d v d d cclk/scl clatch /adr1 or1n or1p ol1n ol1p or2n or2p ol2n ol2p top view (not to scale) agnd avdd filtr agnd l f agnd avdd ol3p pd/rst dsdata4 a v d d agnd mclki/xi mclko/xo ad193x dgnd dgnd a d c 2 r n a d c 2 r p a d c 2 l n a d c 2 l p a d c 2 r n a d c 1 r p a d c 1 l n a d c 1 l p c m a v d d ol3n or3p or3n ol4p ol4n or4p or4n differential output n c n c n c n c v s u p p l y v s e n s e v d r i v e agnd figure 21. differential output 64-lead lqfp (ad1937, ad1939) 44 43 42 41 40 39 38 37 36 35 34 33 25 26 27 28 17 18 19 20 21 22 23 24 9 10 11 12 1 2 3 4 5 6 7 8 60 59 58 57 56 51 50 49 55 54 53 52 14 15 16 13 29 30 31 32 48 47 46 45 64 63 62 61 d v d d d b c l k d l r c l k d s d a t a 3 d s d a t a 2 d s d a t a 1 a s d a t a 2 a s d a t a 1 a b c l k a l r c l k c o u t c i n d v d d cclk clatch nc or1 nc ol1 nc or2 nc ol2 top view (not to scale) agnd avdd filtr agnd l f agnd avdd ol3 pd/rst dsdata4 a v d d agnd mclki/xi mclko/xo ad193x dgnd dgnd a d c 2 r n a d c 2 r p a d c 2 l n a d c 2 l p a d c 2 r n a d c 1 r p a d c 1 l n a d c 1 l p c m a v d d nc or3 nc ol4 nc or4 nc single-ended output n c n c n c n c v s u p p l y v s e n s e v d r i v e agnd figure 22. single-ended output output 64-lead lqfp (ad1935) preliminary preliminary
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 21 of 30 application circuits figure 23. typical adc input filter circuit figure 24. typical dac output filter circuit (single-ended, non-inverting) figure 25. typical dac output filter circuit (single-ended, inverting) figure 26. typical dac output filter circuit (differential)
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 22 of 30 figure 27. recommended loop filters for lrclk or mclk pll reference. figure 28. recommended 3.3v regulator circuit (64-lead versions)
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 23 of 30 register definitions register format global address r/w register address data bit 23:17 16 15:8 7:0 table 16 note 1: the format is the same for i 2 c and spi. note 2: global address for the ad193x series is 0x04, shifted left 1 bit due to the r/w bit. note 3: in i 2 c, adr0 and adr1 are ored into bits 17 an d 18 to provide multiple chip addressing. note 4: all registers are reset to 0, except for the dac volume registers which are set to full volume. register addresses and functions address function 0 pll and clock control 0 1 pll and clock control 1 2 dac control 0 3 dac control 1 4 dac control 2 5 dac individual channel mutes 6 dac 1l vol control 7 dac 1r vol control 8 dac 2l vol control 9 dac 2r vol control 10 dac 3l vol control 11 dac 3r vol control 12 dac 4l vol control 13 dac 4r vol control 14 adc control 0 15 adc control 1 16 adc control 2 table 17
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 24 of 30 pll and clock control registers pll and clock control 0 bit value function description 0 0 1 normal operation power down pll power down 2:1 00 01 10 11 input 256 (x 44.1 or 48khz) input 384 (x 44.1 or 48khz) input 512 (x 44.1 or 48khz) input 768 (x 44.1 or 48khz) mclk pin functionality (pll active) 4:3 00 01 10 11 xtal oscillator enabled 256xfs vco output 512xfs vco output off mclk_o pin 6:5 00 01 10 11 mclk dlrclk alrclk reserved pll input 7 0 1 disable: adc and dac idle enable: adc and dac active internal mclk enable table 18 pll and clock control 1 bit value function description 0 0 1 pll clock mclk dac clock source select 1 0 1 pll clock mclk adc clock source select 2 0 1 enabled disabled on-chip voltage reference 3 0 1 not locked locked pll lock indicator (read only) 7:4 0000 reserved table 19
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 25 of 30 dac control registers dac control 0 bit value function description 0 0 1 normal power down power down 2:1 00 01 10 11 32/44.1/48 khz 64/88.2/96 khz 128/176.4/192 khz reserved sample rate 5:3 000 001 010 011 100 101 110 111 1 0 8 12 16 reserved reserved reserved sdata delay (bclk periods) 7:6 00 01 10 11 stereo (normal) tdm (daisy chain) dac aux mode (adc, dac tdm coupled) dual-line tdm serial format table 20 dac control 1 bit value function description 0 0 1 latch in mid cycle (normal) latch in at end of cycle (pipeline) bclk active edge (tdm in) 2:1 00 01 10 11 64 (2 channels) 128 (4 channels) 256 (8 channels) 512 (16 channels) bclks per frame 3 0 1 left low left high lrclk polarity 4 0 1 slave master lrclk master/slave 5 0 1 slave master bclk master/slave 6 0 1 dbclk pin internally generated bclk source 7 0 1 normal inverted bclk polarity table 21
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 26 of 30 dac control 2 bit value function description 0 0 1 unmute mute master mute 2:1 00 01 10 11 flat 48 khz curve 44.1 khz curve 32 khz curve deemphasis (32/44.1/48 khz mode only) 4:3 00 01 10 11 24 20 reserved 16 word width 5 0 1 non-inverted inverted dac output polarity 7:6 00 reserved table 22 dac individual channel mutes bit value function description 0 0 1 unmute mute dac 1 left mute 1 0 1 unmute mute dac 1 right mute 2 0 1 unmute mute dac 2 left mute 3 0 1 unmute mute dac 2 right mute 4 0 1 unmute mute dac 3 left mute 5 0 1 unmute mute dac 3 right mute 6 0 1 unmute mute dac 4 left mute 7 0 1 unmute mute dac 4 right mute table 23 dac volume controls bit value function description 7:0 0 1-254 255 no attenuation -3/8 db per step full attenuation dac volume control table 24
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 27 of 30 adc control registers adc control 0 bit value function description 0 0 1 normal power down power down 1 0 1 off on highpass filter 2 0 1 unmute mute adc 1l mute 3 0 1 unmute mute adc 1r mute 4 0 1 unmute mute adc 2l mute 5 0 1 unmute mute adc 2r mute 7:6 00 01 10 11 32/44.1/48 64/88.2/96 128/176.4/192 reserved output sample rate table 25 adc control 1 bit value function description 1:0 00 01 10 11 24 20 reserved 16 word width 4:2 000 001 010 011 100 101 110 111 1 0 8 12 16 reserved reserved reserved sdata delay (bclk periods) 6:5 00 01 10 11 stereo tdm (daisy chain) adc aux mode (adc, dac tdm coupled) reserved serial format 7 0 1 latch in mid cycle (normal) latch in at end of cycle (pipeline) bclk active edge (tdm in) table 26.
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 28 of 30 adc control 2 bit value function description 0 0 1 50/50 (allows 32/24/20/16 bclk/channel) pulse (32 bclk/channel) lrclk format 1 0 1 drive out on falling edge (def) drive out on rising edge bclk polarity 2 0 1 left low left high lrclk polarity 3 0 1 slave master lrclk master/slave 5:4 00 01 10 11 64 128 256 512 bclks per frame 6 0 1 slave master bclk master/slave 7 0 1 abclk pin internally generated bclk source table 27
preliminary technical data ad1935/ad1936/ad1937/ad1938/ad1939 rev. pr i | page 29 of 30 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 figure 29. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters figure 30. 64-lead low profile quad flat package [lqfp] (st-64) dimensions shown in millimeters esd caution esd (electrostatic discharge) sensitiv e device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on de vices subjected to high ener gy electrostatic discharges. therefore, proper esd precautions are recommended to av oid performance degradation or loss of functionality.
ad1935/ad1936/ad1937/ad1938/ad1939 preliminary technical data rev. pr i | page 30 of 30 ordering guide ad193x products temperature package (ambient) package description package option ad1935xstz C40c to +105c 64-lead lqfp, se out, spi control w/ reg st-64 ad1935xstzrl C40c to +105c 64-lead lqfp, se ou t, spi control w/ reg st-64 on 13 reels ad1936xstz C40c to +105c 48-lead lqfp, se out, i 2 c control st-48 ad1936xstzrl C40c to +105c 48-lead lqfp, se out, i 2 c control st-48 on 13 reels ad1937xstz C40c to +105c 64-lead lqfp, diff out, i 2 c control st-64 ad1937xstzrl C40c to +105c 64-lead lqfp, diff out, i 2 c control st-64 on 13 reels ad1938xstz C40c to +105c 48-lead lq fp, se out, spi control st-48 ad1938xstzrl C40c to +105c 48-lead lqfp, se out, spi control st-48 on 13 reels ad1939xstz C40c to +105c 64-lead lq fp, diff out, spi control st-64 ad1939xstzrl C40c to +105c 64-lead lqfp, di ff out, spi control st-64 on 13 reels eval-ad1935eb ad1935 evaluation board EVAL-AD1936EB ad1936 evaluation board eval-ad1937eb ad1937 evaluation board eval-ad1938eb ad1938 evaluation board eval-ad1939eb ad1939 evaluation board note: all parts are lead-free table 28. ordering guide ? 2005 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the proper ty of their respective companies. printed in the u.s.a.

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